? semiconductor components industries, llc, 2016 july, 2016 ? rev. 12 1 publication order number: MC100LVELT22/d MC100LVELT22 3.3v?dual lvttl/lvcmos to differential lvpecl translator description the MC100LVELT22 is a dual lvttl/lvcmos to differential lvpecl translator. due to lvpecl (low voltage positive ecl) levels, only +3.3v and ground is required. the small 8?lead package outline with low skew dual gate design makes the MC100LVELT22 ideal for applications which require translation of a clock and/or data signal. features ? 350 ps typical propagation delay ? <100 ps output?to?output skew ? flow through pinouts ? the 100 series contains temperature compensation ? lvpecl operating range: v cc = 3.15 v to 3.45 v with gnd = 0 v ? when unused ttl input is left open, q output will default high ? these are pb?free devices *for additional marking information, refer to application note and8002/d. marking diagrams* kr22 alyw soic?8 d suffix case 751 tssop?8 dt suffix case 948r 1 8 1 8 see detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. ordering information www. onsemi.com kvt22 alyw 1 8 (note: microdot may be in either location) a = assembly location l = wafer lot y = year w = work week m = date code = pb?free package 1 8
MC100LVELT22 www. onsemi.com 2 1 2 3 45 6 7 8 d0 gnd v cc q0 d1 q1 q1 q0 lvpecl lvttl/ lvcmos figure 1. 8?lead pinout (top view) and logic diagram pin function table 1. pin description qn, qn lvpecl differential outputs d0, d1 lvttl/lvcmos inputs v cc positive supply gnd ground table 2. attributes characteristics value internal input pulldown resistor n/a internal input pullup resistor n/a esd protection human body model machine model > 4 kv > 200 v moisture sensitivity, indefinite time out of drypack (note 1) soic?8 tssop?8 level 1 level 3 flammability rating oxygen index: 28 to 34 ul 94 v?0 @ 0.125 in transistor count 164 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 7 v v i input voltage gnd = 0 v v i v cc 7 v i out output current continuous surge 50 100 ma ma t a operating temperature range ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm so?8 so?8 190 130 c/w c/w jc thermal resistance (junction?to?case) std bd so?8 41 to 44 5% c/w ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm tssop?8 tssop?8 185 140 c/w c/w jc thermal resistance (junction?to?case) std bd tssop?8 41 to 44 5% c/w t sol wave solder pb?free <2 to 3 sec @ 260 c 265 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 2. jedec standard multilayer board ? 2s2p (2 signal, 2 power)
MC100LVELT22 www. onsemi.com 3 table 4. lvpecl dc characteristics v cc = 3.3 v; gnd = 0.0 v (note 3) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i cc power supply current 28 28 29 ma v oh output high voltage (note 4) 2275 2420 2275 2420 2275 2420 mv v ol output low voltage (note 4) 1490 1680 1490 1680 1490 1680 mv note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. 3. output parameters vary 1:1 with v cc . v cc can vary 0.15 v. 4. outputs are terminated through a 50 ohm resistor to v cc ?2 v. table 5. lvttl/lvcmos input dc characteristics v cc = 3.3 v; t a = ?40 c to 85 c (note 5) symbol characteristic min typ max unit condition i ih input high current 20 a v in = 2.7 v i ihh input high current 100 a v in = v cc i il input low current ?0.2 ma v in = 0.5 v v ik input clamp diode voltage ?1.2 v i in = ?18 ma v ih input high voltage 2.0 3.3 v v il input low voltage 0 0.8 v note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. 5. v cc can vary 0.15 v. table 6. ac characteristics v cc = 3.3 v; gnd = 0.0 v (note 6) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency 350 mhz t plh propagation delay (note 7) 200 350 600 200 350 600 200 350 600 ps t skew skew output?to?output part?to?part 30 100 400 30 100 400 30 100 400 ps t jitter random clock jitter (rms) 2.1 1.1 1.9 1.6 ps t jit( ) additive rms phase jitter f c = 50 mhz, integration range: 12 khz to 20 mhz (see figure 2) 219 fs t r /t f output rise/fall time (20?80%) 200 550 200 500 200 500 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. 6. v cc can vary 0.15 v. outputs are terminated through a 50 resistor to v cc ? 2 v. 7. specifications for standard ttl input signal.
MC100LVELT22 www. onsemi.com 4 figure 2. typical MC100LVELT22 phase noise plot at f carrier = 50 mhz, v cc = 3.3 v, 25 c the above phase noise data was captured using agilent e5052a/b. the data displays the input phase noise and output phase noise used to calculate the additive phase jitter at a specified integration range. the additive rms phase jitter contributed by the device (integrated between 12 khz and 20 mhz) is 219 fs. the additive rms phase jitter performance of the translator is highly dependent on the phase noise of the input source. to obtain the most precise additive phase noise measurement, it is vital that the source phase noise be notably lower than that of the dut. if the phase noise of the source is greater than the noise floor of the device under test, the source noise will dominate the additive phase jitter calculation and lead to an incorrect negative result for the additive phase noise within the integration range. the figure above is a good example of the MC100LVELT22 source generator phase noise having a significantly lower floor than the dut and results in an additive phase jitter of 219 fs. additive rms phase jitter = rms phase jitter of output 2 ? rms phase jitter of input 2 219 fs 587.92 fs 2 545.23 fs 2 figure 2 was created with measured data from agilent?e5052b signal source analyzer using on semiconductor phase noise explorer web tool. this free application enables an interactive environment for advanced phase noise and jitter analysis of timing devices and clock tree designs. to see the performance of MC100LVELT22 beyond conditions outlined in this datasheet, please visit the on semiconductor green point design tools homepage.
MC100LVELT22 www. onsemi.com 5 figure 3. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package shipping ? MC100LVELT22dg soic?8 (pb?free) 98 units / rail MC100LVELT22dr2g soic?8 (pb?free) 2500 / tape & reel MC100LVELT22dtg tssop?8 (pb?free) 100 units / rail MC100LVELT22dtrg tssop?8 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1672/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
MC100LVELT22 www. onsemi.com 6 package dimensions soic?8 nb case 751?07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
MC100LVELT22 www. onsemi.com 7 package dimensions dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c 0.80 1.10 0.031 0.043 d 0.05 0.15 0.002 0.006 f 0.40 0.70 0.016 0.028 g 0.65 bsc 0.026 bsc l 4.90 bsc 0.193 bsc m 0 6 0 6 seating plane pin 1 1 4 85 detail e b c d a g detail e f m l 2x l/2 ?u? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 8x ref k ident k 0.25 0.40 0.010 0.016 tssop?8 dt suffix case 948r?02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane -w-. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 MC100LVELT22/d eclinps is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.
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